Time Petri Net Unfoldings and Hardware Veriication

Real-time applications require hardware components to be predictable in terms of their temporal characteristics. For this reason synchronous (clocked) circuits have traditionally been used in real-time systems. With the advent of submicron technologies the role of asynchronous techniques in designing hardware platforms for real-time systems will dramatically increase. Yet the lack of eecient formal techniques and algorithms to validate self-timed system designs for their timing dependability appears to worry most practitioners. This paper describes a novel approach to timing analysis and veriication of asynchronous circuits with bounded delays. The method is based on the time-driven unfolding of a time Petri net model of a circuit. Each reachable state, together with its timing constraints is represented implicitly. It is used to detect potential hazards in asynchronous circuits consisting of micropipeline components and logic gates.